View CS532306_569517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS5323 Three-Phase Buck Controller with 5-Bit DAC
The CS5323 is a three-phase step down controller that incorporates all control functions required to power next generation processors. Proprietary multi-phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. Enhanced V2TM control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. The multi-phase architecture reduces input and output filter ripple, allowing for a reduction in filter size and inductor values with a corresponding increase in the output inductor current slew rate. Features * Enhanced V2 Control Method * 5-Bit DAC with 1.0% Tolerance * Adjustable Output Voltage Positioning * Programmable Frequency Set by Single Resistor * 200 kHz to 800 kHz Operation (Per Phase) * Current Sensed through Sense Resistors, or Buck Inductors * Adjustable Current Sense Threshold * Hiccup Mode Current Limit * Over-Voltage Protection through Synchronous MOSFET's * Individual Current Limits for Each Phase * On-Board Current Sense Amplifiers * 3.3 V, 1.0 mA Reference Output * 5.0 V and/or 12 V Operation * On/Off Control (through COMP Pin)
http://onsemi.com
20 1 SO-20L DW SUFFIX CASE 751D
PIN CONNECTIONS AND MARKING DIAGRAM
ROSC COMP VFB VDRP CS1 CS2 CS3 CSREF ILIM REF 1 VCC GATE1 GATE2 GATE3 GND VID4 VID3 VID2 VID1 VID0
CS5323 AWLYWW
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS5323GDW20 CS5323GDWR20 Package SO-20L SO-20L Shipping 37 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. 7
1
Publication Order Number: CS5323/D
CS5323
12 VIN D1 5 VIN C5 1.0 F ENABLE R10 8.0 k C4 0.1 F C11 2.0 nF R6 7.5 k R1 10 NCP5351 R12 75 k U2 ROSC COMP VFB VDRP CS1 CS2 R13 C22 .01 F C21 .01 F R15 30.1 k R16 30.1 k R17 30.1 k C23 C24 10 k CS3 CSREF ILIM REF VCC GATE1 GATE2 D3 C19 1.0 F BAS40LT1 U3 NCP5351 C18 Q3 1.0 F MTD3302 MTP75N06HD C17 .01 F MTP75N06HD CO CST TG DRN U1 Q2 BAS40LT1 1.0 F MTD3302 Q1 L1 300 nH C4 +
C13 3 x 16S0180M
C12 1.0 nF
L2 850 nH
VOUT
EN VS BG Gnd
R9 1.0 k
C28 1.0 nF
+ C16 8x 4SP560M
CS5323
GATE3 Gnd VID4 VID3 VID2 VID1 VID0 VID0
L3 850 nH
CO CST TG DRN
Q4
C20 3x 10 F
.01 F .01 F
D5 C27 1.0 F BAS40LT1
EN VS BG Gnd C26
R14 2.7 k C25 0.1 F R18 1.0 k
VID1 VID2 VID3 VID4
1.0 F MTD3302
Q5 L4
MTP75N06HD
NCP5351 EN CO VS CST TG BG Gnd DRN
U4
850 nH Q6
R19 10 k
Figure 1. Application Diagram, 12 V to 1.7 V Converter
http://onsemi.com
2
CS5323
MAXIMUM RATINGS*
Rating Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range ESD Susceptibility (Human Body Model) 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 230 peak -65 to +150 2.0 Unit C C C kV
MAXIMUM RATINGS
Pin Number 1 2 3 4 5-7 8 9 10 11-15 16 17-19 20 Pin Symbol ROSC COMP VFB VDRP CS1-CS3 CSREF ILIM REF VID0-4 Gnd GATE 1-3 VCC VMAX 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 0V 16 V 16 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V 0V -0.3 V -0.3 V ISOURCE 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 0.4 A, 1.0 s, 100 mA DC 0.1 A, 1.0 s, 25 mA DC N/A ISINK 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 50 mA 1.0 mA N/A 0.1 A, 1.0 s, 25 mA DC 0.4 A, 1.0 s, 100 mA DC
http://onsemi.com
3
CS5323
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 85C; 4.7 V < VCC < 14 V; CGATE = 100 pF,
RR(OSC) = 53.6 k, CCOMP = 0.1 F, CREF = 0.1F, DAC Code 10000, CVCC = 0.1 F, ILIM 1.0 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit
Voltage Identification DAC (0 = Connected to VSS; 1 = Open or Pull-up to 3.3 V) Accuracy (all codes) VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VID4, VID3, VID2, VID1, VID0 VID4, VID3, VID2, VID1, VID0 - 1.064 1.089 1.114 1.139 1.163 1.188 1.213 1.238 1.262 1.287 1.312 1.337 1.361 1.386 1.411 1.436 1.460 1.485 1.510 1.535 1.559 1.584 1.609 1.634 1.658 1.683 1.708 1.733 1.757 1.782 1.807 1.832 1.00 25 3.15 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850 1.25 50 3.30 1.086 1.111 1.136 1.162 1.187 1.212 1.237 1.263 1.288 1.313 1.338 1.364 1.389 1.414 1.439 1.465 1.490 1.515 1.540 1.566 1.591 1.616 1.641 1.667 1.692 1.717 1.742 1.768 1.793 1.818 1.843 1.869 1.50 100 3.45 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V k V Measure VFB = COMP 1.0 %
Input Threshold Input Pull-up Resistance Pull-up Voltage
http://onsemi.com
4
CS5323
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 85C; 4.7 V < VCC < 14 V; CGATE = 100 pF, RR(OSC) = 53.6 k, CCOMP = 0.1 F, CREF = 0.1F, DAC Code 10000, CVCC = 0.1 F, ILIM 1.0 V; unless otherwise specified.)
Characteristic Voltage Feedback Error Amplifier VFB Bias Current (Note 2) COMP Source Current COMP Sink Current COMP Discharge Threshold Voltage Transconductance Output Impedance Open Loop DC Gain Unity Gain Bandwidth PSRR @ 1 kHz COMP Max Voltage COMP Min Voltage Hiccup Latch Discharge Current COMP Discharge Ratio PWM Comparators Minimum Pulse Width Channel Start Up Offset Measured from CSx to GATE(H) with 60 mV step between CSx and CSREF V(CS1) = V(CS2) = V(CS3) = V(VFB) V(CSREF) = 0 V; Measure V(COMP) when GATE (H) 1, 2 switch high - 0.3 350 0.4 500 0.5 ns V Note 3 0.01 F - VFB = 1.8 V; COMP Open; DAC = 00000 VFB = 1.9 V; COMP Open; DAC = 00000 - - 0.9 V < VFB < 1.9 V COMP = 0.5 V to 2.0 V; VFB = 1.8 V; DAC = 00000 COMP = 0.5 V to 2.0 V; VFB = 1.9 V; DAC = 00000 - -10 A < ICOMP < +10 A - 17.6 15 15 0.20 - - 60 - - 2.4 - 2.0 4.0 19.0 30 30 0.27 32 2.5 90 400 70 2.7 0.1 5.0 6.0 20.6 60 60 0.34 - - - - - - 0.2 10 10 A A A V mmho M dB kHz dB V V A - Test Conditions Min Typ Max Unit
GATEs High Voltage Low Voltage Rise Time GATE Fall Time GATE Oscillator Switching Frequency Switching Frequency Switching Frequency ROSC Voltage Phase Delay Adaptive Voltage Positioning VDRP Offset Maximum VDRP Voltage Current Share Amp to VDRP Gain CS1 = CS2 = CS3 = CSREF, VFB = COMP Measure VDRP - COMP |(CS1 = CS2 = CS3) - CREF| = 50 mV, VFB = COMP, Measure VDRP - COMP - -20 360 2.7 - 465 3.0 20 570 3.5 mV mV V/V Rising edge only ROSC = 53.6 k Note 3 ROSC = 32.4 k Note 3 ROSC = 16.2 k - 220 300 600 - 105 250 400 800 1.00 120 280 500 1000 - 135 kHz kHz kHz V deg Measure VCC - GATEx, IGATEx = 1.0 mA Measure GATEx, IGATEx = 1.0 mA 1.0 V < GATE < 8.0 V; VCC = 10 V 8.0 V > GATE > 1.0 V; VCC = 10 V - - - - 1.2 0.25 30 30 2.1 0.50 60 60 V V ns ns
2. The VFB Bias Current changes with the value of ROSC per Figure 4. 3. Guaranteed by design. Not tested in production.
http://onsemi.com
5
CS5323
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 85C; 4.7 V < VCC < 14 V; CGATE = 100 pF, RR(OSC) = 53.6 k, CCOMP = 0.1 F, CREF = 0.1F, DAC Code 10000, CVCC = 0.1 F, ILIM 1.0 V; unless otherwise specified.)
Characteristic Current Sensing and Sharing CS1-CS3 Input Bias Current CSREF Input Bias Current Current Sense Amplifier Gain Current Sense Amp Mismatch (The sum of gain and offset errors) Current Sense Amplifiers Input Common Mode Range Limit Current Sense Input to ILIM Gain Current Limit Filter Slew Rate ILIM Bias Current Single Phase Pulse by Pulse Current Limit: V(CSx) - V(CSREF) Current Share Amplifier Bandwidth Reference Output VREF Output Voltage General Electrical Specifications VCC Operating Current VCC Start Threshold VCC Stop Threshold VCC Hysteresis VFB = COMP(no switching) GATEs switching, COMP charging GATEs stop switching, COMP discharging GATEs not switching, COMP not charging - 4.05 3.75 100 23 4.60 4.4 200 28 4.70 4.65 300 mA V V mV 0 mA < I(VREF) < 1.0 mA 3.2 3.3 3.4 V Note 4 V(CSx) = V(CSREF) = 0 V - - 0 < (CSx - CSREF) < 50 mV Note 4 0.25 V < 1.20 V Note 4 0 < ILIM < 1.0 V - - - 3.7 -5.0 0 5.0 7.5 - 75 0.2 0.6 4.2 - - 6.5 15 0.1 105 2.0 2.0 4.7 5.0 VCC - 2 8.0 40 1.0 115 A A V/V mV V V/V mV/s A mV Test Conditions Min Typ Max Unit
1.0
-
-
mHz
4. Guaranteed by design. Not tested in production.
http://onsemi.com
6
CS5323
PACKAGE PIN DESCRIPTION
PACKAGE PIN # 20 Lead SO Wide 1 2 3 PIN SYMBOL ROSC COMP VFB FUNCTION A resistor from this pin to ground sets operating frequency and VFB bias current. Output of the error amplifier and input for the PWM comparators. Voltage Feedback Pin. To use Adaptive Positioning, set the light load offset voltage by connecting a resistor between VFB and CSREF. The resistor and the VFB bias current determine the offset. For no adaptive positioning connect VFB directly to CSREF. Current sense output for adaptive voltage positioning (AVP). The level of this pin above the DAC voltage is proportional to the output current. Connect a resistor from this pin to VFB to set AVP or leave this pin open for no AVP. Current sense inputs. Connect current sense network for the corresponding phase to each CSx pin. Reference for Current Sense Amplifiers. To balance input offset voltages between the inverting and noninverting inputs of the Current Sense Amplifiers, connect a resistor between CSREF and the output voltage. The value should be 1/3 of the value of the resistors connected to the CSx pins. Sets the threshold for hiccup mode current limit. Connect to reference through a resistive divider. Reference output. Decouple with 0.1 F. Voltage ID DAC inputs. These pins are internally pulled up to 3.3 V if left open. IC Gnd. GATE drive signal. Power for IC.
4
VDRP
5-7
CS1-CS3
8 9 10 11-15 16 17-19 20
CSREF ILIM REF VID0-VID4 Gnd GATE1-3 VCC
http://onsemi.com
7
CS5323
VCC VCC REF VID0 VID1 VID2 VID3 VID4 CO1
OVIC
VCC ILIM - DACOUT
Stop + Start
3.3 V REF PH 1 Reset Dominant S - +
GATE
DAC
4.6 V 4.4 V
Set Dominant
R
PWMC2
- +
CO2
R + MAXC2 - FAULT 0.44 V PH 3
RESC
CS1
0.27 V
CS2
+
CSA2
-
CO2 VITotal CO3 DACOUT
- PWMC3 + CO3 + MAXC3 - - + FAULT CO3 OFFSET 0.44 V FAULT +
x1.5
+
AVPA
EA
FAULT
Gnd
VDRP
COMP
Figure 2. Block Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
900 800 700 Frequency, kHz 600 500 400 300 200 100 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 80 VFB Bias Current, A 60 40 20 80
ROSC Value, k
Figure 3. Oscillator Frequency
http://onsemi.com
8
+ -
CSREF
5 A
-
CS3
CSA3
- +
-
1
2
1
2
-
- +
- CO1 CSA1 +
R
Current Source Gen
Reset Dominant
CO2
S
Reset Dominant
-
S + -
+
+
FAULT
-
+
- +
PWMC1
CO1
MAXC1
R + -
0.44 V
FAULT PH 2 S GATE
GATE
BIAS
PH 1 DACOUT OSC PH 2 PH 3
VFB ROSC
ROSC Value, k
Figure 4. VFB Bias Current vs. ROSC Value
CS5323
APPLICATIONS INFORMATION FIXED FREQUENCY MULTI-PHASE CONTROL In a multi-phase converter, multiple converters are connected in parallel and are switched on at different times. This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. The CS5323 uses a three-phase, fixed frequency, enhanced V2 architecture. Each phase is delayed 120 from the previous phase. Normally the GATE transitions high at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal and the output ripple trip the PWM comparator and bring the GATE low. Once the GATE goes low, it will remain low until the beginning of the next oscillator cycle. While the GATE is high, the enhanced V2 loop will respond to line and load transients. Once the GATE is low, the loop will not respond again until the beginning of the next cycle. Therefore, constant frequency, enhanced V2 will typically respond within the off-time of the converter. The enhanced V2 architecture measures and adjusts current in each phase. An additional input (CX) for inductor current information has been added to the V2 loop for each phase as shown in Figure 5. comparator rises and terminates the pwm cycle. If the inductor starts the cycle with a higher current the PWM cycle will terminate earlier providing negative feedback. The CS5323 provides a CX input for each phase, but the CSREF, VFB and COMP inputs are common to all phases. Current sharing is accomplished by referencing all phases to the same VFB and COMP pins, so that a phase with a larger current signal will turn off earlier than phases with a smaller current signal. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. If the COMP pin is held steady and the inductor current changes there must also be a change in the output voltage. Or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as
DV + RS CSA Gain DI CSA Gain.
The single-phase power stage output impedance is;
Single Stage Impedance + DV DI + RS
SWNODE
L
RL RS
CSX
+
CSA
The multi-phase power stage output impedance is the single-phase output impedance divided by the number of phases. The output impedance of the power stage determines how the converter will respond during the first few s of a transient before the feedback loop has repositioned the COMP pin. The peak output current of each phase can also be calculated from;
V * VFB * VOFFSET Ipkout (per phase) + COMP RS CSA Gain
+ + +
OFFSET CSREF
VOUT
+
VFB DACOUT
+ E.A. +
+
PWMCOMP
COMP
Figure 5. Enhanced V2 Feedback and Current Sense Scheme
The inductor current is measured across RS, amplified by CSA and summed with the OFFSET and Output Voltage at the non-inverting input of the PWM comparator. The inductor current provides the PWM ramp and as inductor current increases the voltage on the positive pin of the pwm
Figure 6 shows the step response of a single phase with the COMP pin at a fixed level. Before T1 the converter is in normal steady state operation. The inductor current provides the pwm ramp through the Current Share Amplifier. The pwm cycle ends when the sum of the current signal, voltage signal and OFFSET exceed the level of the COMP pin. At T1 the output current increases and the output voltage sags. The next pwm cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the VFB pin and the cycle ends at T2. After T2 the output voltage remains lower than at light load and the current signal level is raised so that the sum of the current and voltage signal is the same as with the original load. In a closed loop system the COMP pin would move higher to restore the output voltage to the original level.
http://onsemi.com
9
CS5323
considered when setting the ILIM threshold. If a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in Figure 5.
Current Sharing Accuracy
VFB (VOUT)
SWNODE
CSA Out
COMP - Offset CSA Out + VFB T1 T2
Figure 6. Open Loop Operation Inductive Current Sensing
For lossless sensing current can be sensed across the inductor as shown below in Figure 7. In the diagram, L is the output inductance and RL is the inherent inductor resistance. To compensate the current sense signal the values of R1 and C1 are chosen so that L/RL = R1 x C1. If this criteria is met the current sense signal will be the same shape as the inductor current, the voltage signal at Cx will represent the instantaneous value of inductor current and the circuit can be analyzed as if a sense resistor of value RL was used as a sense resistor (RS).
SWNODE L C1 RL VOUT CSREF VFB DACOUT COMP
E.A. +
PCB traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. For accurate current sharing, the current sense inputs should sense the current at the same point for each phase and the connection to the CSREF should be made so that no phase is favored. (In some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance.) The total current sense resistance used for calculations must include any pcb trace between the CS inputs and the CSREF input that carries inductor current. Current Sense Amplifier Input Mismatch and the value of the current sense element will determine the accuracy of current sharing between phases. The worst case Current Sense Amplifier Input Mismatch is 5 mV and will typically be within 3 mV. The difference in peak currents between phases will be the CSA Input Mismatch divided by the current sense resistance. If all current sense elements are of equal resistance a 3 mV mismatch with a 2 m sense resistance will produce a 1.5 A difference in current between phases.
Operation at > 50% Duty Cycle
R1 CSX
+ CSA
+ + + +
OFFSET
For operation at duty cycles above 50% Enhanced V2 will exhibit subharmonic oscillation unless a compensation ramp is added to each phase. A circuit like the one on the left side of Figure 8 can be added to each current sense network to implement slope compensation. The value of R1 can be varied to adjust the ramp size.
GATE(L)X Switch Node
PWMCOMP
3k
R1
25 k CSX
Figure 7. Lossless Inductive Current Sensing with Enhanced V2
1.0 nF 0.1 F MMBT2222LT1 Slope Comp Circuit
.01 F CSREF
When choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0.39% per C. The increase in winding resistance at higher temperatures should be
Existing Current Sense Circuit
Figure 8. External Slope Compensation Circuit
http://onsemi.com
10
CS5323
Ramp Size and Current Sensing
Because the current ramp is used for both the PWM ramp and to sense current, the inductor and sense resistor values will be constrained. A small ramp will provide a quick transient response by minimizing the difference over which the COMP pin must travel between light and heavy loads, but a steady state ramp of 25 mVP-P or greater is typically required to prevent pulse skipping and minimize pulse width jitter. For resistive current sensing the combination of the inductor and sense resistor values must be chosen to provide a large enough steady state ramp. For large inductor values the sense resistor value must also be increased. For inductive current sensing the RC network must meet the requirement of L/RL = R x C to accurately sense the AC and DC components of the current the signal. Again the values for L and RL will be constrained in order to provide a large enough steady state ramp with a compensated current sense signal. A smaller L, or a larger RL than optimum might be required. But unlike resistive sensing, with inductive sensing small adjustments can be made easily with the values of R and C to increase the ramp size if needed. If RC is chosen to be smaller (faster) than L/RL, the AC portion of the current sensing signal will be scaled larger than the DC portion. This will provide a larger steady state ramp, but circuit performance will be affected and must be evaluated carefully. The current signal will overshoot during transients and settle at the rate determined by R x C. It will eventually settle to the correct DC level, but the error will decay with the time constant of R x C. If this error is excessive it will effect transient response, adaptive positioning and current limit. During transients the COMP pin will be required to overshoot along with the current signal in order to maintain the output voltage. The VDRP pin will also overshoot during transients and possibly slow the response. Single phase overcurrent will trip earlier than it would if compensated correctly and hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents. The waveforms in Figure 9 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of L = 500 nH, RL = 1.6 m, R1 = 20 k and C1 = .01 F. For ideal current signal compensation the value of R1 should be 31 k. Due to the faster than ideal RC time constant there is an overshoot of 50% and the overshoot decays with a 200 s time constant. With this compensation the ILIM pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step.
Figure 9. Inductive Sensing waveform during a Step with Fast RC Time Constant (50 ms/div) Current Limit
Two levels of overcurrent protection are provided. Any time the voltage on a Current Sense pin exceeds CSREF by more than the Single Phase Pulse by Pulse Current Limit, the pwm comparator for that phase is turned off. This provides fast peak current protection for individual phases. The outputs of all the currents are also summed and filtered to compare an averaged current signal to the voltage on the ILIM pin. If this voltage is exceeded, the fault latch trips and the SS capacitor is discharged by a 5 A source until the COMP pin reaches 0.2 V. Then soft-start begins. The converter will continue to operate in this mode until the fault condition is corrected.
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of the normal operation of the enhanced V2 control topology with synchronous rectifiers. The control loop responds to an overvoltage condition within 400 ns, causing the top MOSFET's to shut off, and the synchronous MOSFET's to turn on. This results in a "crowbar" action to clamp the output voltage and prevents damage to the load. The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low.
Transient Response and Adaptive Positioning
For applications with fast transient currents the output filter is frequently sized larger than ripple currents require in
http://onsemi.com
11
CS5323
order to reduce voltage excursions during transients. Adaptive voltage positioning can reduce peak-peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher at light loads to reduce output voltage sag when the load current is stepped up and set lower during heavy loads to reduce overshoot when the load current is stepped up. For low current applications a droop resistor can provide fast accurate adaptive positioning. However at high currents, the loss in a droop resistor becomes excessive. For example; in a 50 A converter a 1 m resistor to provide a 50 mV change in output voltage between no load and full load would dissipate 2.5 Watts. Lossless adaptive positioning is an alternative to using a droop resistor, but must respond quickly to changes in load current. Figure 10 shows how adaptive positioning works. The waveform labeled normal shows a converter without adaptive positioning. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) adaptive positioning the peak to peak excursions are cut in half. In the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. increases the VDRP pin increases proportionally and the VDRP pin current offsets the VFB bias current and causes the output voltage to further decrease. The VFB and VDRP pins take care of the slower and DC voltage positioning. The first few s are controlled primarily by the ESR and ESL of the output filter. The transition between fast and slow positioning is controlled by the ramp size and the error amp compensation. If the ramp size is too large or the error amp too slow there will be a long transition to the final voltage after a transient. This will be most apparent with lower capacitance output filters. Note: Large levels of adaptive positioning can cause pulse width jitter.
Error Amp Compensation
Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits
Figure 10. Adaptive Positioning
The CS5323 uses two methods to provide fast and accurate adaptive positioning. For low frequency positioning the VFB and VDRP pins are used to adjust the output voltage with varying load currents. For high frequency positioning, the current sense input pins can be used to control the power stage output impedance. The transition between fast and slow positioning is adjusted by the error amp compensation. The CS5323 can be configured to adjust the output voltage based on the output current of the converter. The adaptive positioning circuit is designed to select the DAC setting as the maximum output voltage. (Refer to Figure 1 on page 2.) To set the no-load positioning a resistor (R9) is placed between the output voltage and VFB pin. The VFB bias current will develop a voltage across the resistor to decrease the output voltage. The VFB bias current is dependent on the value of ROSC. See Figure 4 on the datasheet. During no load conditions the VDRP pin is at the same voltage as the VFB pin, so none of the VFB bias current flows through the VDRP resistor (R6). When output current
The transconductance error amplifier can be configured to provide both a slow soft-start and a fast transient response. C4 in the main applications diagram controls soft-start. A 0.1 F capacitor with the 30 A error amplifier output capability will allow the output to ramp up at 0.3 V/ms or 1.5 V in 5 ms. R10 is connected in series with C4 to allow the error amplifier to slew quickly over a narrow range during load transients. Here the 30 A error amplifier output capability works against 8 k (R10) to limit the window of fast slewing too 240 mV - enough to allow for fast transients, but not enough to interfere with soft-start. This window will be noticeable as a step in the COMP pin voltage at start-up. The size of this step must be kept smaller than the Channel Start-Up Offset (nominally 0.4 V) for proper soft-start operation. If adaptive positioning is used the R9 and R8 form a divider with the VDRP end held at the DAC voltage during start-up, which effectively makes the Channel Start-Up Offset larger. C12 is included for error amp stability. A capacitive load is required on the error amp output. Use of values less than 1 nF may result in error amp oscillation of several MHz. C11 and the parallel resistance of the VFB resistor (R9) and the VDRP resistor (R6) are used to roll off the error amp gain. C28 adds a zero to the error amp response to boost the phase near the crossover frequency.
UVLO
The CS5323 has one undervoltage lockout function connected to the VCC pin. In applications where the converter is powered from multiple voltages, additional UVLO protection might be required if the voltage powering the controller can turn on before other voltages. For the 12 VIN converter in Figure 1, the CS5323 UVLO function monitors the 5.0 V supply. If the 5.0 V supply comes up before the 12 V supply, the COMP pin will rise until it reaches the upper rail or until the 12 V supply comes up and the converter comes into regulation. If the delay between the 5.0 V and 12 V supplies is too long, soft-start will be compromised. A diode connected from the 12 V supply to the COMP pin can hold the COMP pin down until the 12 V supply starts to come up. Or, if a higher UVLO
http://onsemi.com
12
CS5323
threshold is needed, a circuit like the one in Figure 11 will lock out the converter until the 12 V supply reaches about 7.0 V.
+12 V +5 V 50 k COMP
100 k 100 k
Figure 11. External UVLO Circuit Remote Sense
In some applications that require remote output voltage sensing, there are conditions when the path of the feedback signal can be broken. In a voltage regulator module (VRM) the remote voltage feedback sense point is typically off the module. If the module is powered apart from the intended application, the feedback will be left open. On a motherboard, the feedback path might be broken when the processor socket is left open. Without the feedback connection the output voltage is likely to exceed the intended voltage. To protect the circuit from overvoltage conditions, a resistor can be connected between the local output voltage and the remote sense line as shown in Figure 12.
Local VOUT Remote VOUT
the controller and the output voltage or in the return path of the gate drive. Additional power and ground planes or islands can be added as required for a particular layout. Output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. If required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. Voltage feedback should be taken from a point of the output or the output filter that doesn't favor any one phase. If the feedback connection is closer to one inductor than the others the ripple associated with that phase may appear larger than the ripple associated with the other phases and poor current sharing can result. The current sense signal is typically tens of milli-volts. Noise pick-up should be avoided wherever possible. Current feedback traces should be routed away from noisy areas such as switch nodes and gate drive signals. The paths should be matched as well as possible. It is especially important that all current sense signals be picked off at similar points for accurate current sharing. If the current signal is taken from a place other than directly at the inductor any additional resistance between the pick-off point and the inductor appears as part of the inherent inductor resistance and should be considered in design calculations. Capacitors for the current feedback networks should be placed as close to the current sense pins as practical. DESIGN PROCEDURE
Current Sensing, Power Stage and Output Filter Components
1. Choose the output filter components to meet peak transient requirements. The formula below can be used to provide an approximate starting point for capacitor choice, but will be inadequate to calculate actual values.
DVPEAK + (DI DT) ESL ) DI ESR
Remote Sense Line
100
CSREF Network
VFB Network
Figure 12. Remote Sense Connection Layout Guidelines
With the fast rise, high output currents of microprocessor applications parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. Typically a multi-layer board with at least one ground plane is recommended. If the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to reroute the currents away from the controller. The slots should typically not be placed between
Ideally the output filter should be simulated with models including ESR, ESL, circuit board parasitics and delays due to switching frequency and converter response. Typically both bulk capacitance (electrolytic, Oscon, etc,) and low impedance capacitance (ceramic chip) will be required. The bulk capacitance provides "hold up" during the converter response. The low impedance capacitance reduces steady state ripple and bypasses the bulk capacitance during slewing of output current. 2. For inductive current sensing (only) choose the current sense network RC to provide a 25 mV minimum ramp during steady state operation.
R + (VIN * VOUT) F VOUT VIN C 25 mV
http://onsemi.com
13
CS5323
Then choose the inductor value and inherent resistance to satisfy L/RL = R x C. For ideal current sense compensation the ratio of L and RL is fixed, so the values of L and RL will be a compromise typically with the maximum value RL limited by conduction losses or inductor temperature rise and the minimum value of L limited by ripple current. 3. For resistive current sensing choose L and RS to provide a steady state ramp greater than 25 mV.
L RS + (VIN * VOUT) TON 25 mV
R is RL or RS; IOUT(LIM) is the current limit threshold. For the overcurrent to work properly the inductor time constant (L/R) should be the Current sense RC. If the RC is too fast, during step loads the current waveform will appear larger than it is (typically for a few hundred s) and may trip the current limit at a level lower than the DC limit.
Adaptive Positioning
Again the ratio of L and RL is fixed and the values of L and RS will be a compromise. 4. Calculate the high frequency output impedance (ConverterZ) of the converter during transients. This is the impedance of the Output filter ESR in parallel with the power stage output impedance (PwrstgZ) and will indicate how far from the original level (VR) the output voltage will typically recover to within one switching cycle. For a good transient response VR should be less than the peak output voltage overshoot or undershoot.
DVR + ConverterZ ConverterZ + ESR PwrstgZ ESR PwrstgZ ) ESR CSA Gain 3
7. To set the amount of voltage positioning below the DAC setting at no load connect a resistor (RV(FB)) between the output voltage and the VFB pin. Choose RV(FB) as;
RV(FB) + NL Position VFB Bias Current
See Figure 4 for VFB Bias Current. 8. To set the difference in output voltage between no load and full load, connect a resistor (RV(DRP)) between the VDRP and VFB pins. RV(DRP) can be calculated in two steps. First calculate the difference between the VDRP and VFB pin at full load. (The VFB voltage should be the same as the DAC voltage during closed loop operation.) Then choose the RV(DRP) to source enough current across RV(FB) for the desired change in output voltage.
DVV(DRP) + IOUTFL R CS to VDRP Gain
where:
PwrstgZ + RS
Multiply the converterZ by the output current step size to calculate where the output voltage should recover to within the first switching cycle after a transient. If the ConverterZ is higher than the value required to recover to where the adaptive positioning is set the remainder of the recovery will be controlled by the error amp compensation and will typically recover in 10 - 20 s.
DVR + DIOUT ConverterZ
where: R = RL or RS for one phase; IOUTFL is the full load output current.
RV(DRP) + DVDRP RV(FB) DVOUT
Calculate Input Filter Capacitor Current Ripple
The procedure below assumes that phases do not overlap and output inductor ripple current (P-P) is less than the average output current of one phase. 9. Calculate Input Current
IIN + VOUT IOUT (Efficiency VIN) VOUT (Efficiency VIN) # of Phases
Make sure that VR is less than the expected peak transient for a good transient response. 5. Adjust L and RL or RS as required to meet the best combination of transient response, steady state output voltage ripple and pulse width jitter.
Current Limit
10. Calculate Duty Cycle (per phase).
Duty Cycle +
11. Calculate Apparent Duty Cycle.
Apparent Duty Cycle + Duty Cycle
When the sum of the Current Sense amplifiers (VITOTAL) exceeds the voltage on the ILIM pin the part will enter hiccup mode. For inductive sensing the ILIM pin voltage should be set based on the inductor resistance (or current sense resistor) at max temperature and max current. To set the level of the ILIM pin: 6. VI(LIM) + R IOUT(LIM) CS to ILIM Gain where:
12. Calculate Input Filter Capacitor Ripple Current. Use the chart in Figure 13 to calculate the normalized ripple current (KRMS) based on the reciprocal of Apparent Duty Cycle. Then multiply the input current by KRMS to obtain the Input Filter Capacitor Ripple Current.
Ripple (RMS) + IIN KRMS
http://onsemi.com
14
CS5323
4.00 3.50 Frequency, kHz 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 10 5 1/ Apparent Duty Cycle 15
3. n/a 4. PwrstgZ + RL
ConverterZ +
CSA Gain 3 + 1.5 mW 4.2 3 + 2.1 mW PwrstgZ ESR
PwrstgZ ) ESR + 2.8 mW 1.5 mW ^ 1.0 mW 2.8 mW ) 1.5 mW DVR + 1.0 mW 60 A + 60 mV
5. n/a
Current Limit
Figure 13. Normalized Input Filter Capacitor Ripple Current
6.VI(LIM) + RL
IOUT(LIM) CS to ILIM Gain + 1.5 mW 75 A 6.5 + 731 mV
DESIGN EXAMPLE Choose the component values for lossless current sensing, adaptive positioning and current limit for a 12 V to 1.5 V 60 A converter. The adaptive positioning is chosen 20 mV below the maximum VOUT at no load and 70 mV below the no-load position with 60 A out. The peak output voltage transient is 100 mV max during a 60 A step current. The overcurrent limit is nominally 75 A.
Current Sensing, Power Stage and Output Filter Components
Adaptive Positioning
7. RV(FB) + NL Position VFB Bias Current
+ 20 mV 19 mA ^ 1.00 kW + 2 mW
8. DVDRP + RL
IOUT Current Sense to VDRP Gain 60 A 3 + 360 mV RV(FB) DVOUT 1.00 kW 50 mV + 7.2 kW
RV(DRP) + DVDRP + 360 mV
9. IIN + 1.6 V 60 A + 9.4 A (0.85 12VIN)
1. Assume 1.5 m of output filter ESR. 2. R + (VIN * VOUT) (VOUT VIN) (F
+ (12 * 1.5) (1.5 12) (250 k + 21 kW a Choose 20 kW L RL + .01 mF 20 kW + 200 ms Choose RL + 2.0 mW L + 2 mW 200 ms + 400 nH
C
25 mV) 25 mV)
10. Duty Cycle + (
0.85
1.6 V + 0.16 12 VIN) 3.0 + 0.48
.01 mF
11. Apparent Duty Cycle + 0.16 12. RMS ripple is 9.4 A
1.0 + 9.4 A
http://onsemi.com
15
CS5323
PACKAGE DIMENSIONS
SO-20L DW SUFFIX CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-20L 17 90 Unit C/W C/W
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
L
http://onsemi.com
16
CS5323/D

▲Up To Search▲

Price & Availability of CS532306

	To Download CS532306 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .